description the encoder ic consists of 13 signal photo diode channels and 1 monitor photo diode channel and is used for the optical reading of rotary or linear code carriers (i.e. discs or scales). the photodiodes are accompanied with precision amplifers plus additional circuitry. the monitor channel is used to drive a constant current source for the highly collimated ir illumination system. functional description background the 13 signal channels are set up as: 1. two precision defning signals (a0, a09), which are two 90 electrical shifted sine, cosine signals. these signals are conditioned to be compensated for ofset and gain errors. after conditioning they are on-chip interpolated and computed to a combined absolute 16 bit gray code, together with signal channels a1-a11. 2. 11 analog (a1-a11) channels, which are directly digitized by precision comparators with hysteresis tracking. the digitized signals are called d1-d11. 3. an internal correction and synchronization module allows the composition of a true 16 bit gray code by merging the data bits of (1) and (2) by still keeping the code monotonic. 4. there is a gray code correction feature for this encoder. this gray code correction can be disabled/enabled by the pin korr. 5. the gain and ofset conditioning value of the sine and cosine signals are preloaded on-chip by factory. this will minimize mechanical sensor misalignment error. features ? two sine/cosine true diferential outputs with 1024 periods for unit alignment ? integrated highly collimated illumination system ? 11 digital tracks plus 2 sin/cos tracks generate precise 16 bit gray code ? ultra fast, 1s cycle for serial data output word equals 16mhz ? the 12 bits msb is functionable up to 12000 rpm, 16 bit up to 1000rpm ? msb can be inverted for changing the counting direc - tion ? monitor track for tracking the light level of the led ? watch dog with alarm output pin lerr ? -25 c to + 85 c operating temperature benefts ? no battery or capacitor required for position detection during power failure ? immediate position detection on power up applications ? rotary application up to 16 bits / 360 absolute position ? cost efective solution for direct integration into oem systems ? linear positioning system aeas - 7500 ultra-precision 16 bit gray code absolute encoder module data sheet
signal-channels a1-a11 the photocurrent of the photodiodes is fed into a tran - simpedance amplifer. the analog output of the amplifer has a voltage swing of(dark/light) about 1.3v. every output is transformed by precision comparators into digital signals (d1-d11). the threshold is at vdd/2(=analog-reference), regulated by the monitor channel. monitor channel with led control at pins ledr and lerr the analog output signal of the monitor channel is regu - lated by the led current. an external bipolar transistor(to be connected by user) sets this level to vdd/2 (control voltage at pin ledr). thus the signal swing of each output is symmetrical to vdd/2(=analog-reference) the error bit at pin lerr is triggered if the ve of the internal bipolar transistor is larger than vdd/2 signals channels a0, a09 with signal conditioning and cali - bration these two channels give out a sine and cosine wave, which are 90 degree phase shifted. these signals have amplitudes, which are almost constant due to the led current monitor - ing. due to amplifer mismatch and mechanical misalign - ment the signals have gain and ofset errors. these errors are eliminated by an adaptive signal conditioning circuitry. the conditioning values are on-chip preprogrammed by factory. the analog output signals of a0 and a09 are sup - plied as true-diferential voltage with a peak to peak value of 2.0v at the pins a09p, a09n, a0p, a0n. interpolator for channels a0,a09 the interpolator generates the digital signals d0,d09 and d-1 to d-4. the interpolated signals d-1 to d-4 extend the 12 bit gray code of the signals d11.d0 to form a 16 bit gray code. d0 and d09 are digitized from a0 and a09. the channels a0-a11 and a09 have very high dynamic bandwidth, which allows a real time monotone 12bit gray code at 12000 rpm. the interpolated 16 bit gray code can be used up to 1000rpm only. at more than 1000rpm, only the 12 bit gray code from the msb side can be used. lsb gray code correction (pin korr) this function block synchronizes the switching points for the 11 bit gray code of the digital signals d1 to d11 with d0 and d09 (digitized signal of a0 and a09). the accuracy of the complete 12 bit gray is defned by the precision of the signals d0/d09. as these two signals are generated by the gain and ofset conditioned analog signals a0 and a09, they are very precise. this gray code correction only works for the full 12 bit (4096 steps per revolution). the correction is not for the 4 excess interpolated bits of the 16 bit gray code. gray code correction can be switched on or of by putting the pin korr =1(on) or =0(of ). msbinv and dout pins the serial interface consists of a shift register. the most signifcant bit, msb(d11) will always be sent frst to dout. the msb can be inverted (change code direction) by using pin msbinv. din and nsl pins the serial input din allows the confguration as ring reg - ister for multiple transmissions or for cascading 2 or more encoders. din is the input of the shift register that shifts the data to dout. the nsl pin controls the shift register, to switch it between load (1) or shift(0) mode. under load mode, dout will give the logic of the msb, i.e. d11. under shift mode (0), coupled with the scl, the register will be clocked, and gives out the serial word output bit by bit. as the clock frequency can be up to 16 mhz, the transmis - sion of the full 16 bit word can be done within 1 s. valid data of dout should be read when the scl clock is low. please refer to timing diagram figure 4.
package dimensions notes: 1. for other options of absolute encoder module, please refer to factory. notes: 1. 3rd angle projection 2. dimensions are in millimeters 3. unless specifed otherwise, the tolerances are: xx. C 0.5; xx.x C 0.2; xx.xx C 0.03 4. note: codewheel and readhead mounting tolerances for radial, tangential and z gap are: radial : 50 um tangential : 40um z gap : 50um figure 1. package dimensions device selection guide 1 part number resolution operating temperature (c) output output code dc supply voltage (v) AEAS-7500-1GSG0 16 bit -25 to 85 ssi + 1024 sine/cosine incremental gray code +4.5 to +5.5 c l radial + tangential+ z + z ?
absolute maximum ratings 1, 2 recommended operating condition electrical characteristics electrical characteristics over recommended operating range, typical at t a =25 c and vd = 5v notes: 1. lsb accuracy will also depend on mechanical precision of the shaft, bearings, hub etc. as the aeas-7500 is a detached encoder set as difer - ent from aeas-7000 series, which are modular, where fnal testing, programming and assembly take place at the customer facility, fnal ac - curacies of the encoder cannot be guaranteed by avago. 2. accuracy would be infuenced by installation control and the bearing and shaft type being used. 3. other test conditions to determine accuracy are briefy listed as follows: (a) at nominal radial, tangential and gap position (b) on dual preloaded bearing with absolute assembly total runout of not exceeding 0.01 mm tir (c) both vdd & vdda rc flters placed not more than 20mm from header pins notes: 1. voltage ripple of supply voltage, v ripple , should be within 100mvpp or less for improved accuracy. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. 2. exposure to absolute maximum rating conditions for extended periods may afect reliability. parameter symbol limits units dc supply voltage vd -0.3 to + 6.0 v input voltage v in -0.3 to +vd +0.3 v output voltage v out -0.5 to +vd +0.3 v moisture level (non-condensing) %rh 85 % operating temperature t a -25 to 85 c storage temperature t s - 40 to 100 c parameter symbol values units notes min. typ. max. dc supply voltage vd + 4.5 + 5.0 +5.5 v 1 operating temperature t a - 25 25 +85 c input high level v ih 0.7*vd vd v input low level v lh 0 0.3*vd v parameter symbol condition values units min typ. max total operating current i total 25 ma digital input-pull down current i pd -20 -5 ma digital input-pull up current i pu 30 160 ma digital ouput-h-level v oh i oh = 2 ma vd -0.5 v vd v digital ouput-l-level v ol i ol = - 2 ma 0 0.5 v scl clock frequency f scl 16 mhz duty cycle scl clock t lh t lh = h/(l+h) 0.4 0.6 accuracy within one revolution 1, 2, 3 f scl = 5mhz rpm =80 v ripple <50mvpp 2 bit signal frequency of a0, a09 f a0 , f a09 250 khz
figure 2. pinout confguration notes: 1. internal pu/pd = internal pull-up (typ. 50ua)/ pull-down (typ. 10ua) cmos-transistor-rs no. pin name description function notes 1 nc do not use 2 korr digital-input 1 = gray code correction active cmos, internal pu 3 probe_on digital-input do not use cmos, internal pd 4 pcl digital input positive edge do not use cmos, internal pu 5 stcal digital input positive edge negative edge do not use unnecessarily cmos, internal pd 6 msbinv digital-input 1 = most signifcant bit, msb, inverted cmos, internal pd 7 din digital input shift register input. use for cascading only. cmos, internal pd 8 nsl digital-input shift-register shift (=0) / load(=1) control cmos, internal pu 9 scl digital-input positive edge shift-register clock cmos, internal pu 10 dout digital output shift-register data out (msb frst) cmoss, 2ma 11 do digital output do signal cmos, 2ma 1 dprobe digital output do9 signal cmos, ma 1 vdd supply voltage +v supply digital 1 gnd ground for supply voltage gnd for v supply analog/digital 1 a09p analog output a09 positive(+true diff.) cmos, analog out 16 gnd ground for supply voltage gnd for v supply analog/digital 17 a0p analog output a0 positive(+true diff.) cmos, analog out 18 a09n analog output a09 negative(-true diff.) cmos, analog out 19 vdda supply voltage +v supply analog 0 a0n analog output a0 negative (- true dif) cmos, analog out 1 lerr digital output ir-led current limit signal cmos, ma ledr analog output to be connected by user to the base of a npn tran - sistor with a series resistor as per figure cmos, analog out pin description
6 figure 3. led module dimensions figure 4. timing diagram notes: 1 3rd angle projection 2. dimensions are in millimeters 3. led module spatial misalignment tolerance absolute limits are as follows: (refer to figure 1 for directional indication) (a) radial limit from nominal : 0.4 mm (b) tangential limit from nominal : 0.4 mm (c) led module placement height at z direction : + 1 mm, - 0.5 mm (as long as no contact with codewheel) (d) tilting at xz plane along pda or center line (cl) : 1 degree led module dimensions
7 figure 5. schematic for using aeas-7500 using the aeas-7500 important note: the rc-flter combination, especially on vdda, is used to flter spikes and transients and is strongly recommended. it is advised that the tantalum caps be put as close to the vdd and vdda pins as possible. it is recommended to ground the probe_on pin during normal operation. leave pcl unconnected. a09n and a0n are the negative cosine and sine waves, the negative versions of a09p and a0p. d0 is used to check the d0 signal. d0 is the digitized signal of a0. dprobe is used to check d09, the digitized signal of a09. recommended to be used for testing purpose only. korr is for gray code correction for 12 bits resolution only. msbinv is for user to change between counting up and counting down for a given rotating direction. msb(d11) will always be sent out to dout frst ledr is an internal voltage monitor which is linked to the monitor channel. it should be connected to the base of an npn transistor via a series resistor to control the led bright - ness per the photodiodes need. (refer to figure 5) lerr will be high when the light output perceived by the photo diode array is low, and the led current is under overdrive mode. this is an indicator when light intensity is at a critical stage afecting the performance of the encoder. it is caused either by contamination of the codewheel or led degradation. operation after powering up the unit using vd =+5v and con - necting gnd to ground, trigger input pins nsl and scl using the timing diagram (figure 4). nsl is a control pin for the internal shift register. nsl=1 is load mode while nsl=0 is shift mode for the shift register. when nsl=0 and combined with clock pulses, the serial gray code will be shifted out to dout bit by bit per every clock pulse. valid data of dout should be sampled at the low point of the clock pulses. the 16 bit serial gray code can be tapped out from pin dout, most signifcant bit (d11) frst. the rate of the 16bit gray code serial transfer rate is dependent on the scl clock frequency. the faster the clock, the faster the transfer rate. the maximum clock rate the aeas-7500 can take is 16 mhz, which means the entire 16 bit gray code can be serially transferred out in 1 us. whenever nsl is high (load mode), the dout will have the logic of the msb (d11). after nsl goes low, the number of bits being transferred out will depend on the number of clock pulses given to scl. the default is 16 clock pulses for the 16 bit gray code. analog-outputs msbin v pcl probe_o n korr ler r lerr d0 10r min 100 tantal 0r to r tantal min vd d vd d (c's optional) di n ns l sc l dou t gnd vd gnd vd (+v) application -logic korr probe_o n a09n gnd vdda a0 p a0 n a09p led r pcl msbin v dou t scl di n ns l vd d dprob e d0 d0 9 configuration and probe control stcal stca l ir - led 7r bc86b
ordering information AEAS-7500-1GSG0 single-turn, -25 to +85 o c, detached encoder set, 5v, se - rial, 16 bit note: for alignment process, please refer to avago technologies website for application note or contact factory. for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, pte. in the united states and other countries. data subject to change. copyright ? 2006 avago technologies pte. all rights reserved. 5989-3095en - march 29, 2006
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